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Tuesday, March 10 • 4:15pm - 6:00pm
Engineering Workshop Breakout: HPC (High-Performance Computing)

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4:15 – 4:35 Impact of GPU Accelerated Computing on Cloud Services, Han Vanholder, Senior Product Manager, NVidia We will provide an overview of the NVIDIA GPU Accelerated Computing Platform and highlight some of the latest developments. We will discuss GPU’s impact on data analytics, deep learning, and high performance computing. We will also touch on how the data center is morphing into a heterogeneous ecosystem that has multiple types of CPUs (x86, ARM64, POWER) and how high performance server interconnects like NVLink promise to revolutionize single node performance.


4:35-5:00 Open Processor Specification and Instruction Set, Thomas Sohmers,  CEO, Rex  Computing  This talk will be covering the future of open processor specifications within the Open Compute Project and the development of REX Computing's HPC focused "Neo64" Instruction Set Architecture, which is to be open sourced. REX is building a HPC focused 64-bit 256-core implementation of this ISA, and a full node design built around the existing OpenRack standard, designed to meet the requirements for exascale systems, with a 10x improvement in power efficiency compared to todays state of the art.  REX believes that by open sourcing its ISA (free as in freedom and beer) will allow other companies to develop robust solutions that have freely available software tools and binary compatibility. REX will also show that this new business model is something that can be profitably done, and encourage better and faster development within the HPC community.


5:00 - 5:20 -  Simulation and Co-Design for HPC, Arun Rodrigues, Sandia Labs The performance characteristics of high performance computers are continuously evolving. Satisfying the ever-greater demands of computer based simulation requires supercomputers of unparalleled power and complexity. To meet these needs requires examination of new ways of organizing hardware, new architectures, and new programming models. Understanding the impact of architectural and application level design choices requires careful modeling of future systems using a variety of simulation techniques, including analytical models, abstract state-machine models, and detailed cycle-accurate models. To meet these requirements, we have developed the Structural Simulation Toolkit (SST), a modular, parallel, multi-scale simulation toolkit that includes a variety of models for processor, network, and memory components. The SST is being used in a number of investigations including abstract memory interfaces, network protocol offload, multi-level memory, photonic networks, and processing-in-memory.

Arun Rodrigues is a Principal Member of the Technical Staff at Sandia National Labs in the Scalable Computer Architecture Group. He received his PhD in Computer Engineering from the University of Notre Dame in 2006. His research interests are in advanced memory architectures and computer architecture simulation.


5:20 – 5:35 - Open Discussion on Upcoming Submissions Part 2,  Devashish Paul and Thomas Sohmers, Co Chairs OCP HPC Topics that will be covered in this include, but not limited to: X86 based low latency computing, DSP + ARM computing, FPGA based low latency Server, Scalable GPU with low latency interconnect,  Top of Rack Switching, Low latency NIC , Open Silicon Interconnect Spec etc

5:35 - 5:50 - IP Solutions for HPC and Open Compute futures - Ravi Thumarakuddy

5:50 – 6:00 pm Wrap up Conclusion, Next Steps


Ravi Swaminathan

VP & GM, Emerging Storage Solutions, SanDisk

Han Vanholder

Senior Product Manager, NVIDIA

Tuesday March 10, 2015 4:15pm - 6:00pm
San Jose Convention Center 150 W San Carlos St, San Jose, CA 95113

Attendees (8)